1. Technical Field
The present invention relates to a semiconductor device and its method of fabrication, and more particularly, to a semiconductor device having storage nodes and its method of fabrication.
2. Discussion of the Related Art
With highly integrated semiconductor devices, a design rule is reduced. The process redundancy for the manufacturing of semiconductor devices is also reduced. In particular, as efforts to develop giga-bit devices are made in the case of a dynamic random access memory (DRAM), the importance of a design rule or a process redundancy in the semiconductor fabrication processes and operational characteristics of the devices are increased.
In particular, the capacitor used in the DRAM must ensure not less than a predetermined capacitance in a limited area to provide normal input/output of data or guarantee refresh characteristics. Various types of capacitors have been proposed, such as a trench type, a stack type, or their combination. However, even with efforts to increase the capacitance through structural improvements of the storage nodes, development of a highly integrated next-generation device is limited because of design rule limitations and problems with generally complicated processes. Therefore, a new capacitor structure is needed to overcome these problems. Developing a new structure without depending just on the structural improvements of the storage node, a capacitor over bitline (COB) structure has been proposed to form a storage node after forming a bit line, and used.
FIGS. 1A through 1E are cross-sectional views illustrating a method of fabricating a conventional storage node. The method of fabricating the conventional storage node having the COB structure described as above will be explained in reference to the figures.
As shown in FIG. 1A, a semiconductor substrate 1 having a predetermined lower structure including a transistor (not shown) and a bit line (not shown) is prepared. A lower insulating layer 3 is formed on the substrate 1. The lower insulating layer 3 is patterned, thereby forming first contact holes 4 that expose a predetermined portion of the substrate 1. Buried contact plugs 5 are formed to fill the first contact holes 4. An upper insulating layer 7 is formed on the substrate having the buried contact plugs 5, and is etched, thereby forming second contact holes 8 that expose the buried contact plugs 5 and extend along one direction with a wider contact area than that of the buried contact plugs 5. A buffer conductive layer 9 is formed on the substrate having the second contact holes 8.
As shown in FIG. 1B, the buffer conductive layer 9 is etched until the surface of the upper insulating layer 7 is exposed, thereby forming a buffer conductive layer pattern 9a that fills the second contact holes 8. A process of etching the buffer conductive layer 9 may use an etch back process or a chemical mechanical polishing (CMP) process. The buffer conductive layer pattern 9a is formed to prevent contact failures between the buried contact plug 5 and storage nodes to be formed later.
As shown in FIG. 1C, an etch stop layer 11 and a mold oxide layer 13 are sequentially formed on the substrate having the buffer conductive layer pattern 9a. The etch stop layer 11 may include a silicon nitride layer, and the mold oxide layer 13 may include a silicon oxide layer. The mold oxide layer 13 and the etch stop layer 11 are sequentially patterned, thereby forming storage node contact holes 14 that expose the buffer conductive layer pattern 9a. 
As shown in FIG. 1D, a conformal storage node layer 15 is formed on the semiconductor substrate having the storage node contact holes 14. The storage node layer 15 may include a polycrystalline silicon layer.
As shown in FIG. 1E, the storage node layer 15 is treated using an etch back process until the mold oxide layer is exposed, thereby forming cylinder-shaped storage nodes 15a. After the etching, the remaining mold oxide layer is removed. The removal of the mold oxide layer may be performed using a wet etch process. The wet etch process normally uses an etchant of diluted HF (DHF) or buffered oxide etchants (BOE). In particular, an etchant having an etch rate for the silicon oxide layer of 500 /min. or less is called low advanced low (LAL). The LAL includes two types: LAL 500 and LAL 200, the etch rates of which are 500 /min. and 200 /min. respectively. To remove the mold oxide layer the etchant may be either LAL 500 or LAL 200.
As shown in FIG. 2, which is an enlarged view of an A portion of FIG. 1E, etch residue 17 may exist on bottom surfaces and lower side surfaces of the storage node contact holes 14 after the process of etching the mold oxide layer and the etch stop layer. In this case, if etchant permeates into the storage node contact holes 14 during a wet etch process to remove the remaining mold oxide layer, since the etch residue 17 act as a chemical path, the upper insulating layer 7 and the lower insulating layer 3 below the etch stop layer, and even the bit line of the substrate or the insulating layer surrounding the transistor are etched (see reference numeral a). As a result, the etch stop layer may collapse at the etched portion, and the storage nodes are not supported well at their base due to the etching of the insulating layers. Production yield of these devices then decreases.
After the storage node contact holes are formed, a cleaning process to remove the etch residues may be additionally performed. However, to completely remove the etch residues, time for the cleaning process must be lengthened.
Therefore, there is a need to develop a capacitor and a method for its fabrication having reduced damages to the storage nodes from a wet etch process to remove the mold oxide layer, despite etch residues that may exist between the etch stop layer and the storage nodes inside the storage node contact holes.